Developed based on AMD/Xilinx 40G Ethernet MAC IP, MTU data transmission up to 9000 bytes, AXI4 stream interface, supporting Kintex™ 7 / Virtex™ 7 / UltraScale™ / Ultrade+™ / Zynq UltraScale+™ Series FPGA devices, high bandwidth and low latency, fast data transmission and real-time processing, accurate and efficient data transmission of UDP protocol stack.
Developed based on AMD/Xilinx 40G Ethernet MAC IP, MTU supports up to 9000 bytes of data transmission, standard AXI4 Stream interface, supports AMD/Xilinx Zynq UltraScale+ RFSoC, Zynq UltraScale+ MPSoC, Virtex UltraScale+, Kintex UltraScale+, Artix UltraScale+, Virtex UltraScale, Kintex UltraScale, Virtex 7, Kintex 7, Zynq 7030/7035/7045/7100 Series FPGA devices. The 40G Ethernet with high bandwidth and low latency ensures fast data transmission and real-time processing, while the UDP protocol stack further improves the efficiency and accuracy of data transmission.
We provide you with a fast, reliable, low-cost, and high-performance solution that significantly shortens the time to market and is suitable for high bandwidth, low latency, and high-speed data transmission scenarios.
● Data Center
● Cloud Computing Storage
● AI
● Machine Learning
● Telecommunications
● Industrial Automation
● Internet of Things
● Medical
● Gene Sequencing
● 4K/8K HD Video Transmission
● Scientific Research Experiment
● Financial Transactions
● Test Measurement
● Implement an ARP/IPV4/ICMP/UDP protocol stack that complies with the IEEE802.3 standard based on the OSI layered model.
● Supports ARP for obtaining or sending MAC addresses.
● Supports ICMP for responding to Ping commands.
● ARP responds to all incoming requests, only stores 10 ARP tables.
● No UDP packets are sent if the ARP table is not established.
● 40Gbps Ethernet connection, supporting UDP/IP checksum processing, calculating CRC by the MAC IP.
● Developed based on AMD/Xilinx 40G MAC IP, supporting MTU up to 9000 Bytes and a minimum 64 Bytes data transmission size.
● AXI4 Stream interface for users, with the protocol stack using a clock of 312.5 MHz generated by the MAC IP, and a 40 Gbps data bus width of 256 bits.
The diagram below shows the position of the 40G Ethernet UDP/IP Protocol Stack FPGA IP Core within the system design:
The 40G Ethernet UDP/IP Protocol Stack FPGA IP Core uses standard AXI4-Stream interfaces for both the user interface and the Ethernet MAC + PCS/PMA IP interface. The Ethernet MAC + PCS/PMA can be any third-party IP. In the provided design example, AMD/Xilinx 40G/50G Ethernet Subsystem IP is used.
The evaluation of IP resource consumption adopts AMD Zynq Ultrascale+ MPSoC series FPGA Development Kits/boards, which provides a fully functional design platform for building communication centric Ethernet applications. The AMD Zynq Ultrascale+ MPSoC series FPGA development boards/Kits provides an out of the box hardware platform with reference designs, which can shorten development time and allow you to focus on your target applications.
| Chip Model | Device Series | Frequency (MHz) | CLB Regs | CLB LUTs | CLB | BRAM Tile | URAM | Design Tools | |||
|---|---|---|---|---|---|---|---|---|---|---|---|
| XCZU19EG-FFVC1760-2-I | Zynq Ultrascale+ MPSoC | 312.5 | 16324 | 10050 | 2478 | 5 | 5 | Vivado 2020.1 | |||
Note: Actual IP resource consumption is affected by the consumption of other logical resources during instantiation.
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IP Information
Documentation
40G UDP/IP protocol stack IP Core User Guide
IP Provided Format
Encrypted Netlist
Design Language
Verilog
Development Tool
Vivado 2020.1
Supported Devices
AMD/Xilinx Zynq UltraScale+ RFSoC, Zynq UltraScale+ MPSoC, Virtex UltraScale+, Kintex UltraScale+, Artix UltraScale+, Virtex UltraScale, Kintex UltraScale, Virtex 7, Kintex 7, Zynq 7030/7035/7045/7100
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40G UDP_IP protocol stack IP Core User Guide
2024-11-06Links： AMD Pangomicro AUMO Autonomous Driving
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